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CAT93C66
4-Kb Microwire Serial CMOS EEPROM
FEATURES
High speed operation: 2MHz 1.8V to 5.5V supply voltage range Selectable x8 or x16 memory organization Sequential read Software write protection Power-up inadvertant write protection Low power CMOS technology 1,000,000 Program/erase cycles 100 year data retention Industrial temperature ranges RoHS-compliant 8-pin PDIP, SOIC, TSSOP and 8-pad TDFN packages For Ordering Information details, see page 15.
DESCRIPTION
The CAT93C66 is a 4-Kb CMOS Serial EEPROM device which is organized as either 256 registers of 16 bits (ORG pin at VCC) or 512 registers of 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C66 features sequential read and self-timed internal write with auto-clear. On-chip Power-On Reset circuitry protects the internal logic against powering up in the wrong state.
PIN CONFIGURATION
PDIP (L) SOIC (V, X) TSSOP (Y) TDFN (VP2, ZD4)* CS SK DI DO 1 2 3 4 8 VCC 7 NC 6 ORG 5 GND NC VCC CS SK
FUNCTIONAL SYMBOL
VCC
SOIC (W) 1 2 3 4 8 ORG 7 GND 6 DO 5 DI
ORG CS SK DI CAT93C66 DO
* TDFN 3x3mm (ZD4) package is available only for Die Rev E (not recommended for new designs)
GND
PIN FUNCTION
Pin Name CS SK DI DO VCC GND ORG NC Function Chip Select Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization No Connection
Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization
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CAT93C66
ABSOLUTE MAXIMUM RATINGS(1) Parameters Storage Temperature Voltage on Any Pin with Respect to Ground RELIABILITY CHARACTERISTICS(3) Symbol NEND
(4) (2)
Ratings -65 to +150 -0.5 to +6.5
Units C V
Parameter Endurance Data Retention
Min 1,000,000 100
Units Program/ Erase Cycles Years
TDR
D.C. OPERATING CHARACTERISTICS (NEW PRODUCT, DIE REV. G) VCC = +1.8V to +5.5V, TA=-40C to +85C unless otherwise specified. Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Block Mode, VCC = 5V, 25C
Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16 Mode) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage
Test Conditions fSK = 1MHz, VCC = 5.0V fSK = 1MHz, VCC = 5.0V VIN = GND or VCC, CS = GND ORG = GND VIN = GND or VCC, CS = GND ORG = Float or VCC VIN = GND to VCC VOUT = GND to VCC, CS = GND 4.5V VCC < 5.5V 4.5V VCC < 5.5V 1.8V VCC < 4.5V 1.8V VCC < 4.5V 4.5V VCC < 5.5V, IOL = 2.1mA 4.5V VCC < 5.5V, IOH = -400A 1.8V VCC < 4.5V, IOL = 1mA 1.8V VCC < 4.5V, IOH = -100A
Min
Max 1 500 2 1 1 1
Units mA A A A A A V V V V V V V V
-0.1 2 0 VCC x 0.7 2.4
0.8 VCC + 1 VCC x 0.2 VCC + 1 0.4 0.2
VCC - 0.2
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CAT93C66
D.C. OPERATING CHARACTERISTICS (MATURE PRODUCT, DIE REV. E - Not Recommended for New Designs) VCC = +1.8V to +5.5V, unless otherwise specified. Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16 Mode) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Conditions fSK = 1MHz, VCC = 5.0V fSK = 1MHz, VCC = 5.0V VIN = GND or VCC, CS = GND ORG = GND VIN = GND or VCC, CS = GND ORG = Float or VCC VIN = GND to VCC VOUT = GND to VCC, CS = GND 4.5V VCC < 5.5V 4.5V VCC < 5.5V 1.8V VCC < 4.5V 1.8V VCC < 4.5V 4.5V VCC < 5.5V, IOL = 2.1mA 4.5V VCC < 5.5V, IOH = -400A 1.8V VCC < 4.5V, IOL = 1mA 1.8V VCC < 4.5V, IOH = -100A VCC - 0.2 2.4 0.2 -0.1 2 0 VCC x 0.7 Min Max 3 500 10 10 1 1 0.8 VCC + 1 VCC x 0.2 VCC + 1 0.4 Units mA A A A A A V V V V V V V V
PIN CAPACITANCE TA = 25C, f = 1MHz, VCC = 5V Symbol COUT CIN
Notes: (1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods.
(1) (1)
Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG)
Conditions VOUT = 0V VIN = 0V
Min
Typ
Max 5 5
Units pF pF
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CAT93C66
A.C. CHARACTERISTICS(1) (NEW PRODUCT, DIE REV. G) VCC = +1.8V to +5.5V, TA = -40C to +85C, unless otherwise specified. Limits Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(2) tEW tCSMIN tSKHI tSKLOW tSV SKMAX Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 0.25 0.25 0.25 0.25 2000 Min 50 0 100 100 0.25 0.25 100 5 Max Units ns ns ns ns s s ns ms s s s s kHz
A.C. CHARACTERISTICS (1) (MATURE PRODUCT, DIE REV E - Not Recommended for New Design) Limits Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(2) tEW tCSMIN tSKHI tSKLOW tSV SKMAX
Notes: (1) (2) Test conditions according to "A.C. Test Conditions" table. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods.
Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency
VCC = 1.8V - 5.5V Min 200 0 400 400 1 1 400 10 1 1 1 1 DC 250 Max
VCC = 2.5V - 5.5V Min 100 0 200 200 0.5 0.5 200 10 0.5 0.5 0.5 0.5 DC 500 Max
VCC = 4.5V - 5.5V Min 50 0 100 100 0.25 0.25 100 10 0.25 0.25 0.25 0.25 DC 1000 Max
Units ns ns ns ns s s ns ms s s s s kHz
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CAT93C66
POWER-UP TIMING(1) (2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms
Notes: (1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages Output Load
50 ns
0.4V to 2.4V 0.8V, 2.0V 0.2VCC to 0.7VCC 0.5VCC 4.5V VCC 5.5V 4.5V VCC 5.5V 1.8V VCC 4.5V 1.8V VCC 4.5V
Current Source IOLmax/IOHmax; CL=100pF
DEVICE OPERATION
The CAT93C66 is a 4096-bit nonvolatile memory intended for use with industry standard micropro- cessors. The CAT93C66 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 11-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 12-bit instructions control the reading, writing and erase operations of the device. The CAT93C66 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The serial communication protocol follows the timing shown in Figure 1. INSTRUCTION SET Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Start Bit 1 1 1 1 1 1 1 Address Opcode 10 11 01 00 00 00 00 x8 A8-A0 A8-A0 A8-A0 11XXXXXXX 00XXXXXXX 10XXXXXXX 01XXXXXXX x16 A7-A0 A7-A0 A7-A0 11XXXXXX 00XXXXXX 10XXXXXX 01XXXXXX x8 Data x16 Comments Read Address AN - A0 Clear Address AN - A0 Write Address AN - A0 Write Enable Write Disable Clear All Addresses Write All Addresses The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy "1" into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 8-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). The instruction format is shown in Instruction Set table.
D7-D0
D15-D0
D7-D0
D15-D0
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CAT93C66
Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C66 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). For the CAT93C66, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. The READ instruction timing is illustrated in Figure 2. Erase/Write Enable and Disable The CAT93C66 powers up in the write disable state. Any writing after power-up or after an EWDS (erase/write disable) instruction must first be preceded by the EWEN (erase/write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C66 write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. The EWEN and EWDS instructions timing is shown in Figure 3.
Figure 1. Sychronous Data Timing
tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH
Figure 2. READ Instruction Timing
SK
CS Don't Care AN DI 1 1 0 tPD0 DO HIGH-Z AN-1 A0
Dummy 0
D15 . . . D0 or D7 . . . D0
Address + 1 D15 . . . D0 or D7 . . . D0
Address + 2 D15 . . . D0 or D7 . . . D0
Address + n D15 . . . or D7 . . .
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CAT93C66
Write After receiving a WRITE command (Figure 4), address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C66 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN (Figure 5). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/ busy status of the CAT93C66 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical "1" state.
Figure 3. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
* * ENABLE = 11 DISABLE = 00
Figure 4. Write Instruction Timing
SK tCSMIN CS AN DI 1 0 1 tSV DO HIGH-Z tEW BUSY READY tHZ HIGH-Z AN-1 A0 DN D0 STATUS VERIFY STANDBY
Figure 5. Erase Instruction Timing
SK
CS AN DI 1 1 1 tSV AN-1 A0
STATUS VERIFY tCS
STANDBY
DO
HIGH-Z
tHZ BUSY tEW READY HIGH-Z
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CAT93C66
Erase All Upon receiving an ERAL command (Figure 6), the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C66 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical "1" state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN (Figure 7). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C66 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed.
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY tCS
STANDBY
DI
1
0
0
1
0 tSV tHZ BUSY tEW READY HIGH-Z
DO
HIGH-Z
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY tCSMIN
STANDBY
DI
1
0
0
0
1
DN
D0 tSV tHZ BUSY tEW READY HIGH-Z
DO
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CAT93C66 PACKAGE OUTLINES
8-LEAD 300MIL WIDE PLASTIC DIP (L)
E1
D
E
A2
A
c
A1
L
e b2 b
eB
SYMBOL A A1 A2 b b2 c D E E1 e eB L
MIN 0.38 3.05 0.36 1.14 0.21 9.02 7.62 6.09 7.87 2.92
NOM
MAX 4.57 3.81 0.56 1.77 0.35 10.16 8.25 7.11 9.65 3.81
0.46 0.26 7.87 6.35 2.54 BSC
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) (3) All dimensions are in millimeters. Complies with JEDEC specification MS001 Dimensioning and tolerancing per ANSI Y14.5M-1982.
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CAT93C66
8-LEAD 150 MIL SOIC (V, W)
E1 E
D A q1 e b A1
h x 45 C
L
SYMBOL A1 A b C D E E1 e h L q1
MIN 0.10 1.35 0.33 0.19 4.80 5.80 3.80
NOM
MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00
1.27 BSC 0.25 0.40 0 0.50 1.27 8
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC specification MS-012.
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CAT93C66
8-LEAD 208 MIL SOIC (X)
E
b
D A e A1 L
c
1
SYMBOL A1 A b c D E E1 e L 1
MIN 0.05 0.36 0.19 5.13 7.75 5.13
NOM
MAX 0.25 2.03 0.48 0.25 5.33 8.26 5.38
1.27 BSC 0.51 0 0.76 8
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) All dimensions are in millimeters. Complies with EIAJ specification EDR-7320.
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CAT93C66
8-LEAD TSSOP (Y)
D
8 5
SEE DETAIL A
c E E1
E/2
1
4
GAGE PLANE
PIN #1 IDENT. 0.25 q1 A2 L SEATING PLANE SEE DETAIL A A
e b
A1
SYMBOL A A1 A2 b c D E E1 e L q1
MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00
NOM
MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00
0.90
3.00 6.4 4.40 0.65 BSC 0.60
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC Standard MO-153
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CAT93C66
8-PAD TDFN 2X3 PACKAGE (VP2)
A
E
PIN 1 INDEX AREA
D
A1
A2 A3
D2
SYMBOL A A1 A2 A3 b D D2 E E2 e L
MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20
NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30
MAX 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40
b e 3xe E2
PIN 1 ID
L
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC specification MO-229.
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CAT93C66
8-PAD TDFN 3X3 PACKAGE (ZD4)
3
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC specification MO-229.
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CAT93C66 ORDERING INFORMATION
CAT93C66, DIE REV. G (NEW PRODUCT)*
Prefix CAT
Company ID
Device # Suffix 93C66 V
Package PDIP SOIC, JEDEC SOIC, JEDEC (4) SOIC, EIAJ TSSOP TDFN (2x3mm)
I
Temperature Range I = Industrial (-40C to 85C)
-G
Lead Finish Blank: Matte-Tin G: NiPdAu
T3
Product Number 93C66
L: V: W: X: Y: VP2:
Tape & Reel T: Tape & Reel 2: 2000 units/Reel(4) 3: 3000 units/Reel
Notes: (1) (2) (3) (4) (5) All packages are RoHS-compliant (Lead-free, Halogen-free). The standard lead finish is NiPdAu. The device used in the above example is a CAT93C66VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel). For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C66XI-T2. For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
* For CAT93C66, Die Rev. G (all packages) availability, please contact factory.
CAT93C66, DIE REV. E, MATURE PRODUCT (Not Recommended for New Design)
Prefix CAT
Company ID
Device # Suffix 93C66 V I
Temperature Range I = Industrial (-40C to 85C) A = Automotive (-40C to 105C) E = Extended (-40C to 125C) Package PDIP SOIC, JEDEC SOIC, JEDEC SOIC, EIAJ(5) TSSOP TDFN (3x3mm) Operating Voltage Blank: VCC = 2.5V to 5.5V 1.8: VCC = 1.8V to 5.5V
-1.8
-G T3
Rev E(4)
Die Revision 93C66: E
Product Number 93C66 L: V: W: X: Y: ZD4:
Notes: (1) (2) (3) (4) (5) (6)
Tape & Reel T: Tape & Reel 2: 2000 units/Reel(5) 3: 3000 units/Reel
Lead Finish Blank: Matte-Tin G: NiPdAu
All packages are RoHS-compliant (Lead-free, Halogen-free). The standard finish is NiPdAu. The device used in the above example is a CAT93C66VI-1.8-GT3 (SOIC green package, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, NiPdAu finish, Tape & Reel.) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE.) For additional information, please contact your Catalyst sales office. For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C66XI-T2. For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
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CAT93C66 REVISION HISTORY
Date 05/14/04 Rev. L Comments New Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 and CAT93C86 have been separated into single data sheets Add Die Revision ID Letter Update Features Update Description Update Pin Condition Add Functional Diagram Update Pin Function Update D.C. Operating Characteristics Update Pin Capacitance Update Instruction Set Update Device Operation Update Ordering Information Update Revision History Update Rev Number Update Features Update Pin Configuration / Packages Update Functional Symbol Update Pin Functions Update D.C. Operating Characteristics (VCC Range) Add Package Drawings Update Example of Ordering Information Remove "Die Rev E" from the title Update Pin Configuration / Packages Update Absolute Maximum Rating Update Reliability Characteristics Update D.C. Operating Characteristics Added A.C. Characteristics for Die Rev G Rearrange / Format Text and Figures Added Example of Ordering Information for Die Rev G Update separate DC Characteristics for Die Rev. G and Die Rev. E. Updated Example of Ordering Information Update note on page 1 Update D.C. Operating Characteristics (New Product, Die Rev. G) Update Ordering Information - CAT93C66, Die Rev. G (New Product)
10/13/06
M
11/17/06
N
12/07/06 04/03/07
O P
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(c) 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Document No: 1089 Revision: P Issue date: 04/03/07

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